Technical Field
The present disclosure relates to an input/output circuit to which an external voltage that is higher than a power supply voltage of the input/output circuit section may be applied, that may pulled up or pulled down to the external voltage, and that has a tolerant function used in signal interface section of a semiconductor integrated circuit.
Related Art
In signal interfaces used between semiconductor integrated circuits, there are cases in which a signal interface between semiconductor integrated circuits having different power supply voltages (namely, different signal levels (for example, 3V and 5V)) may be required. In such cases, it is typical to use, as the signal interface of the semiconductor integrated circuit at the low voltage side, an input/output circuit that have a tolerant function that can receive an external voltage that is higher than the power supply voltage, or that can pull up or pull down the signal.
Conventionally, as an input/output circuit having a tolerant function, for example, Japanese Patent Application Laid-Open (JP-A) No. 2005-260587 discloses an input/output circuit of a semiconductor integrated circuit device. In JP-A No. 2005-260587 a bi-directional or output tri-state buffer circuit 1, which is the input/output circuit of the semiconductor integrated circuit device, includes a Pch main Tr (PMOS transistor) 2, Nch main Tr (NMOS transistors) 3 and 4, an output PAD 5, a floating well charging circuit 7, a PchTr (PMOS transistor) 9 having a floating well, a transistor gate 10 configured by a PchTr and an NchTr having floating wells, an EB-PAD potential determination section 21, a bias voltage generating section 22, a power supply potential/bias voltage switching circuit 23, a NAND gate 41, a NOR gate 42, and an inverter IV 43. The bi-directional or output tri-state buffer circuit 1 receives inputs of an input signal IN and an enable signal EB.
The EB-PAD potential determination section 21 of the bi-directional or output tri-state buffer circuit 1 is connected to the enable signal EB and the output PAD 5, and determines the state of the circuit based on the signal level of the enable EB signal and on the PAD potential from the output PAD 5. The EB-PAD potential determination section 21 then outputs a switching signal in accordance with the result of this determination to the bias voltage generating section 22 and the power supply potential/bias voltage switching circuit 23. On the other hand, the bias voltage generating section 22 is connected to an output power supply voltage VDDIO, and outputs a generated output potential Vbias to the power supply potential/bias voltage switching circuit 23. Furthermore, the power supply potential/bias voltage switching circuit 23 is connected to the output power supply voltage VDDIO and the bias voltage generating section 22, and outputs either the VDDIO voltage or the bias voltage Vbias to a gate of the PchTr9, based on the switching signal from the EB-PAD potential determination section 21. As a result, in the output tri-state buffer circuit 1, in a disenable state, the PAD potential is pulled up to an external potential VTT from an L potential or from an H level.
In addition, JP-A No. 2006-157081 discloses an input/output circuit having a tolerant function. In JP-A No. 2006-157081, tri-state output circuit 1 that serves as the input/output circuit includes a one-shot pulse generator circuit 10, an OE/PAD potential determination circuit 20, a bias circuit 30, a floating well charging circuit 40, a transfer gate 50, a 2-input NAND circuit 61, an inverter 62, a 2-input NOR circuit 63, P-MOS transistors 64 and 65, N-MOS transistors 66 and 67, and a resistor 68. The tri-state output circuit 1 outputs an input signal from an output pad PADo which is input from the input terminal A.
In this tri-state output circuit 1, the P-MOS transistor 65 drives the output pad PADo based on a predetermined signal, the P-MOS transistor 64 controls the potential of a node connected to a gate of the P-MOS transistor 65, and the one-shot pulse generator circuit 10 outputs pulses having a predetermined time width in a case in which a transition in the signal level of a predetermined signal has occurred. Moreover, the bias circuit 30 generates a bias voltage used to control the P-MOS transistor 64 during the period in which the pulses are being output, and applies this bias voltage to a gate of the P-MOS transistor 64. As a result, pull-up is performed swiftly in the tri-state output circuit 1, and any increase in current consumption is suppressed.
In conjunction with recent increases in the scale of integration and diversification of function and the like, suppressing current consumption in a semiconductor integrated circuit has become an urgent issue. Input/output circuits between semiconductor integrated circuits are no exception to this, and suppressing current consumption or suppressing the scale of the circuitry continues are required. Although an object of the bi-directional or output tri-state buffer circuit 1 disclosed in JP-A No. 2005-260587 is to suppress current consumption, it is still necessary to use circuits such as the EB-PAD potential determination section 21, the bias voltage generating section 22, and the power supply voltage/bias voltage switching circuit 23 and the like. Accordingly, there is considerable room for improvement from the standpoint of suppressing current consumption and suppressing increases in the scale of the circuitry. In addition, although an object of the tri-state output circuit 1 disclosed in JP-A No. 2006-157081 to reduce current consumption, it is still necessary to use the one-shot pulse generator circuit 10, the OE/PAD potential determination circuit 20, the bias circuit 30, and the floating well charging circuit 40 and the like. Accordingly, there is considerable room for improvement from the standpoint of suppressing current consumption and suppressing increases in the scale of the circuitry.